Flash memory is commonly employed in computer and microprocessor systems as electrically erasable programmable read-only memory (EEPROM) for the non-volatile storage of data. A common structure for flash memory devices is an array of memory cells comprising silicon nitride as a charge-trapping layer within a stacked gate structure formed as a silicon oxide/silicon nitride/silicon oxide (ONO) structure. The name silicon nitride read-only memory or NROM generally refers to such memory devices.
The stacked gate structure includes the ONO structure fabricated on a semiconductor substrate between source and drain regions implanted therein. A control gate is deposited on top of the gate stack. The silicon nitride charge trapping layer is insulated from the semiconductor substrate, the source and drain implants, and the control gate by the silicon oxide in the ONO layer.
Through appropriate biasing of the control gate, the source, and the drain of a memory cell, charge may be injected into or removed from the charge-trapping layer. A memory cell may be read by appropriately biasing the cell to determine the presence or absence of a trapped charge. The presence or absence of a charge represents a logic value stored in the flash memory cell.
Leakage current, e.g., the leakage of injected charge from the charge trapping layer, is a significant factor in determining how long data is retained in an NROM memory cell. At small memory cell sizes, leakage current is often a design limiting parameter. For example, a minimum silicon oxide layer thickness in the ONO layer may be needed to keep leakage current low enough to provide a desired data retention lifetime.
Defects in the insulating oxide layers of a stacked gate structure have an adverse effect on leakage current. A significant cause of damage to the insulating oxide layers is the presence of excessive tunneling currents during device fabrication. After a stacked gate is formed additional processing steps are performed to finish fabrication. For example additional masking and etching may be required to form additional semiconductor structures or to deposit metal or polysilicon interconnects on a semiconductor device. When a device is exposed to plasma processing, e.g., plasma etching, electrical charges may accumulate on the interconnects due to a phenomenon referred to as the ‘antenna effect.’ The accumulated charge on the interconnects creates a voltage difference across the ONO layer of a NROM memory cell. A sufficiently large voltage difference may cause tunneling current to flow through the ONO layer introducing a programming effect and altering the threshold voltage of the memory cell. In addition, large induced tunneling currents may damage the insulating oxides in the stacked gate, causing a decrease in insulation and resulting in increased leakage currents in the memory cells.
Accordingly, a need exists to protect flash memory cells, and NROM memory cells in particular, from induced charge damage during fabrication. The present invention addresses such a need.